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1. introduction this document describes the functionality and electrical specif ication of the nfc controller PN7150. additional documents describing the product functionality further are available for design-in support. refer to the references liste d in this document to get access to the full for full documentation provided by nxp. 2. general description best plugn play and high-performance full nfc solution PN7150 is a full nfc controller solution with integrated firmware and nci interface designed for contactless communication at 13.56 mhz. it is compatible with nfc forum requirements. PN7150 is designed based on learnings from previous nxp nfc device generation. it is the ideal solution for rapidly integrating nf c technology in any application, especially those running o/s envi ronment like linux and android, re ducing bill of material (bom) size and cost, thanks to: ? full nfc forum compliancy (see ref. 1 ) with small form factor antenna ? embedded nfc firmware prov iding all nfc protocols as pre-integrated feature ? direct connection to the main host or microcontroller, by i 2 c-bus physical and nci protocol ? ultra-low power consumpt ion in polling loop mode ? highly efficient integrated power management unit (pmu) allowing direct supply from a battery PN7150 embeds a new generation rf contactless front-end supporting various transmission modes acco rding to nfcip-1 and nfcip-2, iso/iec14443, iso/iec 15693, mifare and felica specifications. it emb eds an arm cortex-m0 microcontroller core loaded with the integrated firmware supportin g the nci 1.0 host communication. it also allows to provide a higher output power by supplying the transmitter output stage from 3.0 v to 4.75 v. the contactless front-end design brings a major performance step-up with on one hand a higher sensitivity and on the ot her hand the capability to work in active load modulation communication enabling the support of small antenna form factor. supported transmission modes are listed in figure 1 . for contactless card functionality, the PN7150 can act autonomously if previously configured by the host in such a manner. PN7150 high performance full nfc forum-compliant controller with integrated firmware and nci interface rev. 3.3 ? 4 july 2016 product data sheet
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 2 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware PN7150 integrated firmware provides an easy integration and validation cycle as all the nfc real-time constraints, protocols and devi ce discovery (polling loop) are being taken care internally. in few nci commands, host sw can configure the PN7150 to notify for card or peer detection and start communicating with them. 3. features and benefits ? includes nxp iso/iec14443-a, innovatr on iso/iec14443-b and nxp mifare crypto1 intellectual property licensing rights ? arm cortex-m0 microcontroller core ? highly integrated demodulator and decoder ? buffered output drivers to connect an antenna with minimum number of external components ? integrated rf level detector ? integrated polling loop for automatic device discovery ? rf protocols supported ? nfcip-1, nfcip-2 protocol (see ref. 8 and ref. 11 ) ? iso/iec 14443a, iso/iec 14443b picc , nfc forum t4t modes via host interface (see ref. 3 ) ? nfc forum t3t via host interface ? iso/iec 14443a, iso/iec 14443b pcd designed according to nfc forum digital protocol t4t platform and iso-dep (see ref. 1 ) ? felica pcd mode ? mifare pcd encryption mechanism (mifare 1k/4k) ? nfc forum tag 1 to 5 (mifare ultralight, je wel, open felica tag, desfire) (see ref. 1 ) ? iso/iec 15693/icode vcd mode (see ref. 9 ) ? supported host interfaces (1) according to iso/iec 18092 (ecma 340) standard. fig 1. PN7150 transmission modes aaa-023871 card (picc) t4t - iso/iec 14443 a t4t - iso/iec 14443 b reader (pcd - vcd) iso/iec 14443 a iso/iec 14443 b iso/iec 15693 mifare 1k / 4k mifare desfire sony felica (1) nfc forum nfc-ip modes p2p active 106 to 424 kbps initiator and target p2p passive 106 to 424 kbps initiator and target nfc forum t3t reader for nfc forum tags 1 to 5
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 3 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware ? nci protocol interface according to nfc forum standardization (see ref. 2 ) ? i 2 c-bus high-speed mode (see ref. 4 ) ? integrated power management unit ? direct connection to a battery (2.3 v to 5.5 v voltage supply range) ? support different hard power-down/standby states activated by firmware ? autonomous mode when host is shut down ? automatic wake-up vi a rf field, internal timer and i 2 c-bus interface ? integrated non-volatile memory to store data and executable code for customization 4. applications ? all devices requiring nfc functionality especi ally those running in an android or linux environment ? tvs, set-top boxes, blu-ray decoders, audio devices ? home automation, gatewa ys, wireless routers ? home appliances ? wearables, remote contro ls, healthcare, fitness ? printers, ip phones, gaming consoles, accessories 5. quick reference data table 1. quick reference data symbol parameter conditions min typ max unit v bat battery supply voltage card emulation and passive ta r g e t ; v ss =0v [1] [2] 2.3- 5.5v reader, active initiator and active target; v ss = 0 v [1] [2] 2.7- 5.5v v dd supply voltage internal supply voltage 1.65 1.8 1.95 v v dd(pad) v dd(pad) supply voltage supply voltage for host interface 1.8 v host supply; v ss =0v [1] 1.65 1.8 1.95 v 3 v host supply; v ss = 0 v [1] 3.0- 3.6v i bat battery supply current in hard power down state; v bat =3.6v; t=25c [3] -1014 ? a in standby state; v bat =3.6v; t=25c -20- ? a in monitor state; v bat = 2.75 v; t = 25 c -- 14 ? a in low-power polling loop; v bat = 3.6 v; t = 25 c; loop time = 500 ms [4] - 150 - ? a pcd mode at typical 3 v [2] -- 190ma i o(vddpad) output current on pin v dd(pad) total current which can be pulled on v dd(pad) referenced outputs -- 15ma
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 4 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware [1] v ss represents v ss(pad) and v ss(tx) . [2] the antenna should be tuned not to exceed this curr ent limit (the detuning effect when coupling with another device must be taken into account). [3] external clock on nfc_clk_xtal1 must be low. [4] see ref. 10 for computing the power consumption as it depends on several parameters. 6. ordering information [1] xx = firmware code variant. 7. marking i th(ilim) current limit threshold current current limiter on v dd(tx) pin; v dd(tx) =3.3v [2] - 180 - ma p tot total power dissipation reader; i vdd(tx) = 100 ma; v bat =5.5v -- 420mw t amb ambient temperature jedec pcb-0.5 ? 30 - +85 ?c table 1. quick reference data ?continued symbol parameter conditions min typ max unit table 2. ordering information type number package name description version PN7150b0hn/c110xx [1] hvqfn40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 ? 6 ? 0.85 mm sot618-1 fig 2. PN7150 package marking (top view) table 3. marking codes type number marking code line a 7 characters used: basic type number: PN7150x where x is the fw variant 05 terminal 1 index area a :7 b1 : 6 aaa-007965 b2 : 6 c : 8
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 5 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware line b1 6 characters used: diffusion batch sequence number line b2 6 characters used: assembly id number line c 7 characters used: manufacturing code including: ? diffusion center code: ? z: ssmc ? s: powerchip (ptct) ? assembly center code: ? s: apk ? rohs compliancy indicator: ? d: dark green; fully compliant rohs and no halogen and antimony ? manufacturing year and week, 3 digits: ? y: year ? ww: week code ? product life cycl e status code: ? x: means not qualified product ? nothing means released product table 3. marking codes ?continued type number marking code
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 6 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 8. block diagram fig 3. PN7150 block diagram aaa-016737 rf detect rf detect cless interface unit sensor demod adc driver txctrl pll bg vmid miscellaneous timers crc coprocessor random number generator clock management unit oscillator 380 khz fracn pll oscillator 40 mhz quartz oscillator cless uart ahb to apb rx codec signal processing tx codec data memory sram eeprom code memory rom eeprom host interface arm cortex m0 memory control i 2 c-bus power management unit battery monitor 4.5 v tx-ldo 1.8 v dsldo
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 7 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 9. pinning information 9.1 pinning fig 4. pinning table 4. pin description symbol pin type [1] refer description i2cadr0 1 i v dd(pad) i 2 c-bus address 0 i.c. 2 - - internally connected; must be connected to gnd i2cadr1 3 i v dd(pad) i 2 c-bus address 1 v ss(pad) 4 g n/a pad ground i2csda 5 i/o v dd(pad) i 2 c-bus data line v dd(pad) 6 p n/a pad supply voltage i2cscl 7 i v dd(pad) i 2 c-bus clock line irq 8 o v dd(pad) interrupt request output v ss 9 g n/a ground ven 10 i v bat reset pin. set the device in hard power down i.c. 11 - - internally connected; leave open v bat2 12 p n/a battery supply volta ge; must be connected to v bat v bat1 13 p n/a battery supply volta ge; must be connected to v bat v dd(tx) 14 p n/a transmitter supply voltage aaa-016738 PN7150 v ss transparent top view terminal 1 index area 1 2 3 4 5 6 7 8 9 10 i2cadr0 i.c. i2cadr1 v ss(pad) i2csda v dd(pad) i2cscl irq v ss ven v ddd v dd v dda v ss v bat i.c. i.c. i.c. v dd(tx_in) tx1 30 29 28 27 26 25 24 23 22 21 20 19 32 18 17 16 15 14 13 12 11 n.c. v ss(tx) tx2 v dd(mid) rxp rxn v dd(tx) v bat1 v bat2 i.c. 31 33 34 35 36 37 38 39 40 n.c. n.c. n.c. n.c. n.c. nfc_clk_xtal1 nfc_clk_xtal2 i.c. i.c. clk_req
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 8 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware [1] p = power supply; g = ground; i = input, o = output; i/o = input/output. 10. functional description PN7150 can be connected on a host controller through i 2 c-bus. the logical interface towards the host baseband is nci-compliant ref. 2 with additional command set for nxp-specific product features. this ic is fully user controllable by the firmware interface described in ref. 5 . moreover, PN7150 provides flexible and inte grated power management unit in order to preserve energy supporting power off mode. in the following chapters you will find also more details about PN7150 with references to very useful application note such as: rxn 15 i v dd negative receiver input rxp 16 i v dd positive receiver input v dd(mid) 17 p n/a receiver reference input supply voltage tx2 18 o v dd(tx) antenna driver output v ss(tx) 19 g n/a contactless transmitter ground n.c. 20 - - not connected tx1 21 o v dd(tx) antenna driver output v dd(tx_in) 22 p n/a transmitter input supply voltage; must be connected to v dd(tx) i.c. 23 - - internally connected; leave open i.c. 24 - - internally connected; leave open i.c. 25 - - internally connected; leave open v bat 26 p n/a battery supply voltage v ss 27 g n/a ground v dda 28 p n/a analog supply voltage; must be connected to v dd v dd 29 p n/a supply voltage v ddd 30 p n/a digital supply voltage; must be connected to v dd n.c. 31 - - not connected n.c. 32 - - not connected n.c. 33 - - not connected n.c. 34 - - not connected n.c. 35 - - not connected nfc_clk_xtal1 36 i v dd oscillator input/pll input nfc_clk_xtal2 37 o v dd oscillator output i.c. 38 - - internally connected; leave open i.c. 39 - - internally connected; leave open clk_req 40 o v dd(pad) clock request pin table 4. pin description ?continued symbol pin type [1] refer description
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 9 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware ? PN7150 user manual ( ref. 5 ): user manual describes the software interfaces (api) based on the nfc forum nci standard. it does give full description of a ll the nxp nci extensions coming in addition to nci standard ( ref. 2 ). ? PN7150 hardware design guide ( ref. 6 ): hardware design guide provides an overview on the different hardware design options offered by the ic and provides guidelines on how to select the most appropriate ones for a given implementation . in particular, this document highlights the different chip power states and how to operate them in order to minimize the average nfc-related power consumption so to enhance the battery lifetime. ? PN7150 antenna and tuning design guide ( ref. 7 ): antenna and tuning design guide provides some guidelines regarding the way to design an nfc antenna for the PN7150 chip. it also explains how to determine the tuni ng/matching network to place between this antenna and the PN7150. standalone antenna performances evaluatio n and final rf system validation (PN7150 + tuning/matching network + nfc antenna within its final environment) are also covered by this document. ? PN7150 low-power mode configuration ( ref. 10 ): low-power mode configuration documentation provides guidance on how PN7150 can be configured in order to reduce current consumption by usin g low-power polling mode. 10.1 system modes 10.1.1 system power modes PN7150 is designed in order to enable the different power modes from the system. fig 5. PN7150 connection aaa-016739 nfcc host interface control host controller battery/pmu antenna matching
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 10 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 2 power modes are specified: full power mode and power off mode. ta b l e 6 summarizes the system power mode of the PN7150 depending on the status of the external supplies available in the system: depending on power modes, some application states are limited: 10.1.2 PN7150 power states next to system power modes defined by the status of the power supplies, the power states include the logical status of th e system thus extend the power modes. 4 power states are specified: monitor, hard power down (hpd), standby, active. table 5. system power modes description system power mode description full power mode the main supply (v bat ) as well as the host interface supply (v dd(pad) ) is available, all use cases can be executed power off mode the system is kept hard power down (hpd) fig 6. system power mode diagram table 6. system power modes configuration v bat ven power mode off x power off mode on off power off mode on on full power mode table 7. system power modes description system power mode allowed communication modes power off mode no communication mode available full power mode reader/writer, card emulation, p2p modes aaa-015871 [ven = off] [v bat = on && v dd(pad) = on ven = on] [v bat = off || ven = off] full power mode power off mode
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 11 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware at application level, the pn71 50 will continuously switch between different states to optimize the current consumptio n (polling loop mode). refer to ta b l e 1 for targeted current consumption in here described states. the PN7150 is designed to allow the host controller to have full control over its functional states, thus of the power consumption of th e PN7150 based nfc solution and possibility to restrict parts of the PN7150 functionality. 10.1.2.1 monitor state in monitor state, the PN7150 will exit it only if the battery voltage recovers over the critical level. battery voltage monitor thresholds show hysteresis behavior as defined in ta b l e 2 7 . 10.1.2.2 hard power down (hpd) state the hard power down state is entered when v dd(pad) and v bat are high by setting ven voltage < 0.4 v. as these signals are under ho st control, the PN7150 has no influence on entering or exiting this state. 10.1.2.3 standby state active state is PN7150?s default state afte r boot sequence in order to allow a quick configuration of PN7150. it is recommended to change the default state to standby state after first boot in order to save power. pn 7150 can switch to standby state autonomously (if configured by host). in this state, PN7150 most blocks including cpu are no more supplied. number of wake-up sources exist to put PN7150 into active state: ? i 2 c-bus interface wake-up event ? antenna rf level detector ? internal timer event when using polling loop (380 khz low-power oscillator is enabled) table 8. PN7150 power states power state name description monitor the PN7150 is supplied by v bat which voltage is below its programmable critical level, ven voltage > 1.1 v and the monitor state is enabled. the system power mode is power off mode. hard power down the PN7150 is supplied by v bat which voltage is above its programmable critical level when monitor state is enabled and PN7150 is kept in hard power down (ven voltage is kept low by host or sw programming) to have the minimum power consumption. the system power mode is in power off. standby the PN7150 is supplied by v bat which voltage is above its programmable critical level when the monitor state is enabled, ven voltage is high (by host or sw programming) and minimum part of PN7150 is kept supplied to enable configured wake-up sources which allow to switch to active state; rf field, host interface. the system po wer mode is full power mode. active the PN7150 is supplied by v bat which voltage is above its programmable critical level when monitor state is enabled, ven voltage is high (by host or sw programming) and the PN7150 internal blocks are supplied. 3 functional modes are defined: idle, target and initiator. the system power mode is full power mode.
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 12 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware if wake-up event occurs, PN7150 will switch to active state. any further operation depends on software configuration and/or wake-up source. 10.1.2.4 active state within the active state, the system is acti ng as an nfc device. the device can be in 3 different functional modes: idle, poller and target. poller mode: in this mode, PN7150 is acting as reader/writer or nfc initiator, searching for or communicating with passive tags or nfc target. once rf communication has ended, PN7150 will switch to active battery mode (that is, switch off rf transmitter) to save energy. poller mode shall be used with 2.7 v < v bat < 5.5 v and ven voltage > 1.1 v. poller mode shall not be used with v bat < 2.7 v. v dd(pad) is within its operational range (see ta b l e 1 ). listener mode: in this mode, PN7150 is acting as a card or as an nfc target. listener mode shall be used with 2.3 v < v bat < 5.5 v and ven voltage > 1.1 v. 10.1.2.5 polling loop the polling loop will sequentially se t PN7150 in differ ent power states (a ctive or standby). all rf technologies supported by PN7150 can be independently enabled within this polling loop. there are 2 main phases in the polling loop: ? listening phase. the PN7150 can be in standby power state or listener mode ? polling phase. the pn71 50 is in poller mode table 9. functional modes in active state functional modes description idle the PN7150 is active and allows host interface communication. the rf interface is not activated. listener the PN7150 is active and is config ured for listening to external device. poller the PN7150 is active and is configured in poller mode. it polls external device
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 13 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware listening phase uses standby power state (when no rf field) and PN7150 goes to listener mode when rf field is detected. when in polling phase, PN7150 goes to poller mode. to further decrease the po wer consumption when runn ing the polling loop, PN7150 features a low-power rf polling. when pn715 0 is in polling phase instead of sending regularly rf command, PN7150 senses with a shor t rf field duration if there is any nfc target or card/tag present. if yes, then it goes back to standard polling loop. with 500 ms (configurable duration, see ref. 5 ) listening phase duration, the average power consumption is around 150 ? a. fig 7. polling loop: all phases enabled aaa-016741 emulation pause type a type b type f @424 type f @212 iso15693 listening phase polling phase
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 14 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware detailed description of polling loop configuration options is given in ref. 5 . 10.2 microcontroller PN7150 is controlled via an embedded arm cortex-m0 microcontroller core. PN7150 features integrated in firmware are referenced in ref. 5 . 10.3 host interface PN7150 provides the support of an i 2 c-bus slave interface, up to 3.4 mbaud. the host interface is waken-up on i 2 c-bus address. to enable and ensure data flow control between PN7150 and host controller, additionally a dedicated interrupt line irq is provided which active state is programmable. see ref. 5 for more information. fig 8. polling loop: low-power rf polling aaa-016743 listening phase emulation pause polling phase
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 15 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 10.3.1 i 2 c-bus interface the i 2 c-bus interface implements a slave i 2 c-bus interface with integrated shift register, shift timing generation and slave address recognition. i 2 c-bus standard mode (100 khz scl), fast mode (400 khz scl) and high-speed mode (3.4 mhz scl) are supported. the mains hardware characteristics of the i 2 c-bus module are: ? support slave i 2 c-bus ? standard, fast and high-speed modes supported ? wake-up of PN7150 on its address only ? serial clock synchronization can be used by PN7150 as a handshake mechanism to suspend and resume serial tr ansfer (clock stretching) the i 2 c-bus interface module meets the i 2 c-bus specification ref. 4 except general call, 10-bit addressing and fast mode plus (fm+). 10.3.1.1 i 2 c-bus configuration the i 2 c-bus interface shares four pins with i 2 c-bus interface also supported by PN7150. when i 2 c-bus is configured in eepr om settings, functionality of interf ace pins changes to one described in ta b l e 1 0 . [1] i2cscl and i2csda are not fail-safe and v dd(pad) shall always be availabl e when using the scl and sda lines connected to these pins. PN7150 supports 7-bit addressi ng mode. selection of the i 2 c-bus address is done by 2-pin configurations on top of a fixed binary header: 0, 1, 0, 1, 0, i2cadr1, i2cadr0, r/w. 10.4 PN7150 clock concept there are 4 different clock sources in PN7150: ? 27.12 mhz clock coming either/or from: ? internal oscillator for 27.12 mhz crystal connection table 10. functionality for i 2 c-bus interface pin name functionality i2cadr0 i 2 c-bus address 0 i2cadr1 i 2 c-bus address 1 i2cscl [1] i 2 c-bus clock line i2csda [1] i 2 c-bus data line table 11. i 2 c-bus interface addressing i2cadr1 i2cadr0 i 2 c-bus address (r/w = 0, write) i 2 c-bus address (r/w = 1, read) 0 0 0x50 0x51 0 1 0x52 0x53 1 0 0x54 0x55 1 1 0x56 0x57
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 16 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware ? integrated pll unit which includes a 1 ghz vco, taking is reference clock on pin nfc_clk_xtal1 ? 13.56 mhz rf clock reco vered from rf field ? low-power oscillator 40 mhz ? low-power oscillator 380 khz 10.4.1 27.12 mhz quartz oscillator when enabled, the 27.12 mhz quartz oscillator applied to PN7150 is the time reference for the rf front end when PN7150 is behaving in reader mode or nfcip-1 initiator. therefore stability of the clock fr equency is an important factor for reliable operation. it is recommended to adopt the circuit shown in figure 9 . ta b l e 1 2 describes the levels of accuracy and stability required on the crystal. [1] this requirement is according to fcc regulat ions requirements. to meet only iso/iec 14443 and iso/iec 18092, then ? 14 khz apply. 10.4.2 integrated pll to make use of external clock when enabled, the pll is designed to generate a low noise 27.12 mhz for an input clock 13 mhz, 19.2 mhz, 24 mhz, 26 mhz, 38.4 mhz and 52 mhz. the 27.12 mhz of the pll is used as the time reference for the rf front end when PN7150 is behaving in reader mode or iso/iec 18092 initiator as well as in target when configured in active communication mode. fig 9. 27.12 mhz crystal oscillator connection table 12. crystal requirements symbol parameter conditions min typ max unit f xtal crystal frequency iso/iec and fcc compliancy - 27.12 - mhz ? f xtal crystal frequency accuracy full operating range [1] ? 100 - +100 ppm all v bat range; t=20c [1] ? 50 - +50 ppm all temperature range; v bat =3.6v [1] ? 50 - +50 ppm esr equivalent series resistance - 50 100 ? c l load capacitance - 10 - pf p xtal crystal power dissipation - - 100 ? w aaa-016745 PN7150 nfc_clk_xtal1 nfc_clk_xtal2 crystal 27.12 mhz c c
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 17 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware the input clock on nfc_clk_ xtal1 shall comply with the.following phase noise requirements for the following input freque ncy: 13 mhz, 19.2 mh z, 24 mhz, 26 mhz, 38.4 mhz and 52 mhz: this phase noise is equivalent to an rms jitter of 6.23 ps from 10 hz to 1 mhz. for configuration of input frequency, refer to ref. 9 . there are 6 pre-programmed and validated frequencies for the pll: 13 mhz, 19.2 mhz, 24 mhz, 26 mhz, 38.4 mhz and 52 mhz. fig 10. input reference phase noise characteristics table 13. pll input requirements coupling: single-ended, ac coupling; symbol parameter conditions min typ max unit f clk clock frequency iso/iec and fcc compliancy -13- mhz -19.2- mhz -24- mhz -26- mhz -38.4- mhz -52- mhz f i(ref)acc reference input frequency accuracy full operating range; frequencies typical values: 13 mhz, 26 mhz and 52 mhz [1] ? 25 - +25 ppm full operating range; frequencies typical values: 19.2 mhz, 24 mhz and 38.4 mhz [1] ? 50 - +50 ppm ? n phase noise input noise floor at 50 khz ? 140 - - db/ hz sinusoidal shape v i(p-p) peak-to-peak input voltage 0.2 - 1.8 v v i(clk) clock input voltage 0 - 1.8 v square shape v i(clk) clock input voltage 0 - 1.8 ? 10 % v aaa-007232 input reference noise floor -140 dbc/hz dbc/hz hz -20dbc/hz input reference noise corner 50 khz
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 18 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware [1] this requirement is according to fcc regulat ions requirements. to meet only iso/iec 14443 and iso/iec 18092, then ? 400 ppm limits apply. for detailed description of clock request mechanisms, refer to ref. 5 and ref. 6 . 10.4.3 low-power 40 mhz ? 2.5 % oscillator low-power osc generates a 40 mhz internal clo ck. this frequency is divided by two to make the system clock. 10.4.4 low-power 380 khz oscillator a low frequency oscillator (lfo) is implem ented to drive a counter (wuc) waking-up PN7150 from standby state. th is allows implementation of low-power reader polling loop at application level. moreover, this 380 khz is used as the reference clock for write access to eeprom memory. 10.5 power concept 10.5.1 pmu functional description the power management unit of PN7150 generates internal supplies required by PN7150 out of v bat input supply voltage: ? v dd : internal supply voltage ? v dd(tx) : output supply voltage for the rf transmitter the figure 11 describes the main blocks available in pmu: 10.5.2 dsldo: dual supply ldo the input pin of the dsldo is v bat . the low drop-out regulator provides v dd required in PN7150. fig 11. pmu functional diagram aaa-016748 v bat v dd nfcc bandgap dsldo txldo v bat1 and v bat2 v dd(tx)
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 19 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 10.5.3 txldo transmitter voltage can be generated by internal ldo (v dd(tx) ) or come from an external supply source v dd(tx) . the regulator has been designed to work in 2 configurations: 10.5.3.1 configuration 1: supply connection in case the battery is used to generate rf field the low drop out regulator has been designed to generate a 3.0 v, 3.3 v or 3.6 v supply voltage to a transmitter with a current load up to 180 ma. the output is called v dd(tx) . the input supply voltage of this regulator is a battery voltage connected to v bat1 pin. v dd(tx) value shall be chosen according to the minimum targeted v bat value for which reader mode shall work. if v bat is above 3.0 v plus the regulator voltage dropout, then v dd(tx) = 3.0 v shall be chosen: if v bat is above 3.3 v plus the regulator voltage dropout, then v dd(tx) = 3.3 v shall be chosen: if v bat is above 3.6 v plus the regulator voltage dropout, then v dd(tx) = 3.6 v shall be chosen: fig 12. v bat1 = v bat2 (between 2.3 v and 5.5 v) aaa-017002 v bat1 nfcc v dd(tx) v dd(tx_in) v bat2 battery v bat 3.0 v1 ? load ? + ?? v dd tx ?? ? ? 3.0 v = 3.0 vv ? bat 2.3 vv dd tx ?? ?? v bat 1 ? load ? ?= v bat 3.3 v1 ? load ? + ?? v dd tx ?? ? ? 3.3 v = 3.3 vv ? bat 2.3 vv dd tx ?? ?? v bat 1 ? load ? ?= v bat 3.6 v1 ? load ? + ?? v dd tx ?? ? ? 3.6 v = 3.6 vv ? bat 2.3 vv dd tx ?? ?? v bat 1 ? load ? ?=
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 20 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware figure 13 shows v dd(tx) offset disabled behavio r for both cases of v dd(tx) programmed for 3.0 v, 3.3 v or 3.6 v. in standby state, whenever v dd(tx) is configured for 3.0 v, 3.3 v or 3.6 v, v dd(tx) is regulated at 2.5 v. figure 14 shows the case where the PN7150 is in standby state. 10.5.3.2 configuration 2: supply connection in case a 5 v supply is used to generate rf field with the use of txldo txldo has also the possibility to generate 4.75 v or 4.5 v supply in case the supply of this regulator is an external 5 v supply. fig 13. v dd(tx) offset behavior fig 14. v dd(tx) behavior when PN7150 is in standby state aaa-014174 5.0 v v bat 2.8 v 3.6 v 3.3 v 3.0 v 4.5 v 3.6 v 3.3 v 3.0 v 2.8 v drop = 1 * load aaa-009463 v bat 2.5 v 2.5 v
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 21 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware figure 16 shows the behavior of v dd(tx) depending on v bat1 value. 10.5.3.3 txldo limiter the txldo includes a current limiter to avoid too high current within tx1, tx2 when in reader or initiator modes. the current limiter block compares an image of the txldo output current to a reference. once the reference is reached, the output cu rrent gets limited whic h is equivalent to a typical output current of 220 ma whatever v bat or v bat1 value in the range of 2.3 v to 5.5 v. 10.5.4 battery voltage monitor the PN7150 features low-power v bat voltage monitor which protects mobile device battery from being discharged below critical levels. when v bat voltage goes below v batcritical threshold, then the PN7150 goes in monitor state. refer to figure 17 for principle schematic of the battery monitor. the battery voltage monitor is enabled via an eeprom setting. at the first start-up, v bat voltage monitor functionality is off and then enabled if properly configured in eeprom. the PN7150 monitors battery voltage continuously. fig 15. v bat1 = 5 v, v bat2 between 2.3 v and 5.5 v fig 16. v dd(tx) behavior when PN7150 is supply using external supply on v bat1 aaa-017003 nfcc external 5 v v bat1 v bat2 battery v dd(tx) v dd(tx_in) aaa-017004 v bat1 drop = 1 * load 4.75 v 5.5 v 4.5 v v dd(tx)
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 22 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware the value of the critical leve l can be configured to 2.3 v or 2.75 v by an eeprom setting. this value has a typical hysteresis around 150 mv. 10.6 reset concept 10.6.1 resetting PN7150 to enter reset, there are 2 ways: ? pulling ven voltage low (hard power down state) ? if v bat monitor is enabled: lowering v bat below the monitor threshold (monitor state, if ven voltage is kept above 1.1 v) reset means resetting the embedded fw execution and the registers values to their default values. part of these default values is de fined from eeprom data loaded values, others are hardware defined. see ref. 5 to know which ones are accessible to tune PN7150 to the application environment. to get out of reset: ? pulling ven voltage high with v bat above v bat monitor threshold if enabled figure 18 shows reset done via ven pin. fig 17. battery voltage monitor principle aaa-013868 system management low power dvdd_cpu v ddd v dd power off vbat monitor registers enable threshold selection power switches power management digital (memories, cpu, etc,...) v bat eeprom
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 23 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware see section 14.2.2 for the timings values. 10.6.2 power-up sequences there are 2 different supplies for PN7150. PN7150 allows these supplies to be set up independently, therefore different power- up sequences have to be considered. 10.6.2.1 v bat is set up before v dd(pad) this is at least the case when v bat pin is directly connected to the battery and when PN7150 v bat is always supplied as soon the system is supplied. as ven pin is referred to v bat pin, ven voltage shall go high after v bat has been set. see section 14.2.3 for the timings values. 10.6.2.2 v dd(pad) and v bat are set up in the same time it is at least the case when v bat pin is connected to a pmu/regulator which also supply v dd(pad) . fig 18. resetting PN7150 via ven pin aaa-015878 host communication possible t boot t w(ven) v en v dd(pad) v bat fig 19. v bat is set up before v dd(pad) aaa-015879 host communication possible t boot t t(vdd(pad)-ven) v en v dd(pad) v bat
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 24 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware see section 14.2.3 for the timings values. 10.6.2.3 PN7150 has been enabled before v dd(pad) is set up or before v dd(pad) has been cut off this can be the case when v bat pin is directly connected to the battery and when v dd(pad) is generated from a pmu. when the battery voltage is too low, then the pmu might no more be able to generate v dd(pad) . when the device gets charged again, then v dd(pad) is set up again. as the pins to select the interface are biased from v dd(pad) , when v dd(pad) disappears the pins might not be correctly biased internally and the information might be lost. therefore it is required to make the ic boot after v dd(pad) is set up again. see section 14.2.3 for the timings values. fig 20. v dd(pad) and v bat are set up in the same time aaa-015881 host communication possible t boot t t(vbat-ven) v en v dd(pad) v bat fig 21. v dd(pad) is set up or cut-off after PN7150 has been enabled t boot t w(ven) v en v dd(pad) v bat t t(vdd(pad)-ven) aaa-015884 host communication possible
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 25 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 10.6.3 power-down sequence 10.7 contactless interface unit PN7150 supports various communication modes at different transfer speeds and modulation schemes. the following chapters give more detailed overview of selected communication modes. remark: all indicated modulation index and modes in this chapter are system parameters. this means that beside the ic settings a suitable antenna tuning is required to achieve the optimum performance. 10.7.1 reader/writer communication modes generally 5 reader/writer communication modes are supported: ? pcd reader/writer for iso/iec 14443a/mifare ? pcd reader/writer for jewel/topaz tags ? pcd reader/writer for felica cards ? pcd reader/writer for iso/iec 14443b ? vcd reader/writer for iso/iec 15693/icode 10.7.1.1 iso/iec 14443a/mifare and jewel/topaz pcd communication mode the iso/iec 14443a/mifare pcd communication mode is the general reader to card communication scheme according to the iso/ iec 14443a specification. this modulation scheme is as well used for commu nications with jewel/topaz cards. figure 23 describes the communication on a physical level, the communication table describes the physical parameters (the numbers take the antenna effect on modulation depth for higher data rates). fig 22. PN7150 power-down sequence aaa-015886 t vbat(l) t > 0 ms t > 0 ms (nice to have) v bat v en v dd(pad)
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 26 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware the contactless coprocessor and the on-c hip cpu of PN7150 handle the complete iso/iec 14443a/mifare rf-protocol, nevert heless a dedicated external host has to handle the application layer communication. 10.7.1.2 felica pcd communication mode the felica communication mode is the general reader/writ er to card communication scheme according to the felica specification. figure 24 describes the communication on a physical level, the communication overview describes the physical parameters. fig 23. iso/iec 14443a/mifare reader/w riter communication mode diagram aaa-016749 nfcc iso/iec 14443a - mifare pcd mode picc (card) iso/iec 14443a - mifare pcd to picc 100 % ask at 106 kbit/s > 25 % ask at 212, 424 or 848 kbit/s modified miller coded picc to pcd, subcarrier load modulation manchester coded at 106 kbit/s bpsk coded at 212, 424 or 848 kbit/s table 14. overview for iso/iec 14443a/mif are reader/writer communication mode communication direction iso/iec 14443a/ mifare/ jewel/ topaz iso/iec 14443a higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s bit length (128/13.56) ? s (64/13.56) ? s (32/13.56) ? s (16/13.56) ? s PN7150 ? picc (data sent by PN7150 to a card) modulation on PN7150 side 100 % ask > 25 % ask > 25 % ask > 25 % ask bit coding modified miller modified miller modified miller modified miller picc ? PN7150 (data received by PN7150 from a card) modulation on picc side subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 mhz/16 13.56 mhz/16 13.56 mhz/16 13.56 mhz/16 bit coding manchester bpsk bpsk bpsk fig 24. felica reader/writer communication mode diagram aaa-016750 nfcc iso/iec 18092 - felica pcd mode picc (card) felica card pcd to picc, 8 - 12 % ask at 212 or 424 kbits/s manchester coded picc to pcd, load modulation manchester coded at 212 or 424 kbits/s
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 27 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware the contactless coprocessor of PN7150 and the on -chip cpu handle th e felica protocol. nevertheless a dedicated external host has to handle the application layer communication. 10.7.1.3 iso/iec 14443b pcd communication mode the iso/iec 14443b pcd communication mode is the general reader to card communication scheme according to the iso/iec 14443b specification. figure 25 describes the communication on a physical level, the communication table describes the physical parameters. table 15. overview for felica reader/writer communication mode communication direction felica felica higher transfer speeds transfer speed 212 kbit/s 424 kbit/s bit length (64/13.56) ? s (32/13.56) ? s PN7150 ? picc (data sent by PN7150 to a card) modulation on PN7150 side 8% ? 12 % ask 8 % ? 12 % ask bit coding manchester manchester picc ? PN7150 (data received by PN7150 from a card) modulation on picc side load modulation load modulation subcarrier frequency no subcarrier no subcarrier bit coding manchester manchester fig 25. iso/iec 14443b reader/writer communication mode diagram aaa-016751 nfcc iso/iec 14443 type b pcd mode picc (card) iso/iec 14443 type b pcd to picc, 8 - 14 % ask at 106, 212, 424 or 848 kbit/s nrz coded picc to pcd, subcarrier load modulation bpsk coded at 106, 212, 424 or 848 kbit/s table 16. overview for iso/iec 14443b reader/writer communication mode communication direction iso/iec 14443b iso/iec 14443b higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s bit length (128/13.56) ? s (64/13.56) ? s (32/13.56) ? s (16/13.56) ? s PN7150 ? picc (data sent by PN7150 to a card) modulation on PN7150 side 8% ? 14 % ask 8 % ? 14 % ask 8 % ? 14 % ask 8 % ? 14 % ask bit coding nrz nrz nrz nrz picc ? PN7150
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 28 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware the contactless coprocessor and the on-c hip cpu of PN7150 handles the complete iso/iec 14443b rf-protocol, nevertheless a dedicated external host has to handle the application layer communication. 10.7.1.4 r/w mode for nfc forum type 5 tag the r/w mode for nfc forum type 5 tag (t5t) is the general reader to card communication scheme accord ing to the iso/iec 15693 s pecification. PN7150 will communicate with vicc (type 5 tag) using only the 26.48 kbit/s with single subcarrier data rate of the vicc. figure 26 and table 17 show the communication schemes used. (data received by PN7150 from a card) modulation on picc side subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 mhz/16 13.56 mhz/16 13.56 mhz/16 13.56 mhz/16 bit coding bpsk bpsk bpsk bpsk table 16. overview for iso/iec 14443b reader/writer communication mode ?continued communication direction iso/iec 14443b iso/iec 14443b higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s bit length (128/13.56) ? s (64/13.56) ? s (32/13.56) ? s (16/13.56) ? s fig 26. r/w mode for nfc forum t5t communication diagram aaa-016752 nfcc iso/iec 15693 vcd mode card (vicc/tag) iso/iec 15693 vcd to vicc, 100 % ask at 26.48 kbit/s pulse position coded vicc to vcd, subcarrier load modulation manchester coded at 26.48 kbit/s table 17. communication overview for nfc forum t5t r/w mode communication direction PN7150 ? vicc (data sent by PN7150 to a tag) transfer speed 26.48 kbit/s bit length (512/13.56) ? s modulation on PN7150 side 10 % ? 30 % or 100 % ask bit coding pulse position mo dulation 1 out of 4 mode vicc ? PN7150 (data received by PN7150 from a tag) transfer speed 26.48 kbit/s bit length (512/13.56) ? s modulation on vicc side subcarrier load modulation subcarrier frequency single subcarrier bit coding manchester
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 29 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 10.7.2 iso/iec 18092, ecma 340 nfcip-1 communication modes an nfcip-1 communication takes place between 2 devices: ? nfc initiator: generates rf field at 13.56 mhz and starts the nfcip-1 communication. ? nfc target: responds to nfc initiator command either in a load modulation scheme in passive communication mode or using a self-generated and self-modulated rf field for active communication mode. the nfcip-1 communication differentiates between active and passive communication modes. ? active communication mode means both the nfc initiator and the nfc target are using their own rf field to transmit data ? passive communication mode means that the nfc target answers to an nfc initiator command in a load modulation scheme. th e nfc initiator is active in terms of generating the rf field. PN7150 supports the active target, active in itiator, passive target and passive initiator communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the nfcip-1 standard. nevertheless a dedicated external host has to handle the application layer communication. 10.7.2.1 active communication mode active communication mode means both the nfc initiator and the nfc target are using their own rf field to transmit data. fig 27. nfcip-1 communication mode aaa-016755 nfcc battery nfc target: passive or active communication modes nfc initiator: passive or active communication modes host nfcc battery host
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 30 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware the following table gives an overview of the active communication modes: [1] this modulation index range is according to nfcip-1 standard. it might be that some nfc forum type 3 cards does not withstan d the full range as based on felica range which is narrow (8 % to 14 % ask). to adjust the index, see ref. 7 . 10.7.2.2 passive communication mode passive communication mode means that the nfc target answers to an nfc initiator command in a load modulation scheme. fig 28. active communication mode aaa-016756 1. nfc initiator starts the communication at selected transfer speed 2. nfc target answers at the same transfer speed nfcc nfc target host power for digital processing nfcc nfc target host power for digital processing nfc initiator host power to generate the field nfc initiator host power to generate the field table 18. overview for active communication mode communication direction iso/iec 18092, ecma 340, nfcip-1 baud rate 106 kbit/s 212 kbit/s 424 kbit/s bit length (128/13.56) ? s (64/13.56) ? s (32/13.56) ? s nfc initiator to nfc target modulation 100 % ask 8 % ? 30 % ask [1] 8% ? 30 % ask [1] bit coding modified miller manchester manchester nfc target to nfc initiator modulation 100 % ask 8 % ? 30 % ask [1] 8% ? 30 % ask [1] bit coding miller manchester manchester
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 31 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware ta b l e 1 9 gives an overview of the passive communication modes: [1] this modulation index range is according to nfcip-1 standard. it might be that some nfc forum type 3 cards does not withstan d the full range as based on felica range which is narrow (8 % to 14 % ask). to adjust the index, see ref. 7 . 10.7.2.3 nfcip-1 framing and coding the nfcip-1 framing and coding in active and passive communication modes are defined in the nfcip-1 standard: iso/iec 18092 or ecma 340. 10.7.2.4 nfcip-1 protocol support the nfcip-1 protocol is not completely described in this document. for detailed explanation of the protocol, refer to the is o/iec 18092 or ecma 340 nfcip-1 standard. however the datalink layer is a ccording to the following policy: fig 29. passive communication mode aaa-016757 1. nfc initiator starts the communication at selected transfer speed 2. nfc target answers using load modulation at the same transfer speed host power for digital processing nfcc nfc target host power for digital processing nfc initiator host power to generate the field nfc initiator host power to generate the field nfcc nfc target table 19. overview for passive communication mode communication direction iso/iec 18092, ecma 340, nfcip-1 baud rate 106 kbit/s 212 kbit/s 424 kbit/s bit length (128/13.56) ? s (64/13.56) ? s (32/13.56) ? s nfc initiator to nfc target modulation 100 % ask 8 % ? 30 % ask [1] 8% ? 30 % ask [1] bit coding modified miller manchester manchester nfc target to nfc initiator modulation subcarrier load modulation load modulation load modulation subcarrier frequency 13.56 mhz/16 no subcarrier no subcarrier bit coding manchester manchester manchester
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 32 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware ? transaction includes initializ ation, anticollision methods and data transfer. this sequence must not be interrupted by another transaction ? psl shall be used to change the speed between the target selection and the data transfer, but the speed should not be changed during a data transfer 10.7.3 card communication modes PN7150 can be addressed as nfc forum t3 t and t4t tags. this means that PN7150 can generate an answer in a load modulation scheme according to the iso/iec 14443a, iso/iec 14443b and the sony felica interfac e description. remark: PN7150 does not support a complete card protocol. this has to be handled by the host controller. ta b l e 2 0 , table 21 and ta b l e 2 2 describe the physical parameters. 10.7.3.1 nfc forum t4t, iso/iec 14443acard mode 10.7.3.2 nc forum t4t, iso/iec 14443b card mode table 20. overview for nfc forum t4t, iso/iec 14443a card mode communication direction iso/iec 14443a iso/iec 14443a higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s bit length (128/13.56) ? s (64/13.56) ? s (32/13.56) ? s pcd ? PN7150 (data received by PN7150 from a card) modulation on pcd side 100 % ask > 25 % ask > 25 % ask bit coding modified miller modified miller modified miller PN7150 ? pcd (data sent by PN7150 to a card) modulation on PN7150 side subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 mhz/16 13.56 mhz/16 13.56 mhz/16 bit coding manchester bpsk bpsk table 21. overview for nfc forum t4t, iso/iec 14443b card mode communication direction iso/iec 14443b iso/iec 14443b higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s bit length (128/13.56) ? s (64/13.56) ? s (32/13.56) ? s pcd ? PN7150 (data received by PN7150 from a reader) modulation on pcd side 8% ? 14 % ask 8 % ? 14 % ask 8 % ? 14 % ask bit coding nrz nrz nrz PN7150 ? pcd (data sent by PN7150 to a reader) modulation on PN7150 side subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 mhz/16 13.56 mhz/16 13.56 mhz/16 bit coding bpsk bpsk bpsk
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 33 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 10.7.3.3 nfc forum t3t, sony felica card mode 10.7.4 frequency interoperability when in communication, PN7150 is generating some rf frequencies. PN7150 is also sensitive to some rf signals as it is looking from data in the field. in order to avoid interference with others rf communication, it is required to tune the antenna and design the board according to ref. 6 . although iso/iec 14443 and iso/iec 18092/ecma 340 allows an rf frequency of 13.56 mhz ? 7 khz, fcc regulation does not allo w this wide spread and limits the dispersion to ? 50 ppm, which is in line with PN7150 capability. table 22. overview for nfc forum t3t, sony felica card mode communication direction felica felica higher transfer speeds transfer speed 212 kbit/s 424 kbit/s bit length (64/13.56) ? s (32/13.56) ? s pcd ? PN7150 (data received by PN7150 from a reader ) modulation on PN7150 side 8% ? 12 % ask 8 % ? 12 % ask bit coding manchester manchester PN7150 ? pcd (data sent by PN7150 to a reader) modulation on picc side load modulation load modulation subcarrier frequency no subcarrier no subcarrier bit coding manchester manchester
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 34 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 11. limiting values [1] the design of the solution shall be done so that fo r the different use cases targeted the power to be dissipated from the field or generated by PN7150 does not exceed this value. 12. recommended operating conditions table 23. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd(pad) v dd(pad) supply voltage supply voltage for host interface -4.35v v bat battery supply voltage - 6 v v esd electrostatic discharge voltage hbm; 1500 ? , 100 pf; eia/jesd22-a114-d -1.5kv cdm; field induced model; eia/jesc22-c101-c -500v t stg storage temperature ? 55 +150 ? c p tot total power dissipation all modes [1] -600mw v rxn(i) rxn input voltage 0 2.5 v v rxp(i) rxp input voltage 0 2.5 v table 24. operating conditions symbol parameter conditions min typ max unit t amb ambient temperature jedec pcb-0.5 ? 30 +25 +85 ?c v bat battery supply voltage battery monitor enabled; v ss =0v [1] 2.3 - 5.5 v card emulation and passive target; v ss =0v [1] [2] 2.3 - 5.5 v reader, active initiator and active target; v ss =0v [1] [2] 2.7 - 5.5 v v dd(pad) v dd(pad) supply voltage supply voltage for host interface 1.8 v host supply; v ss =0v [1] 1.65 1.8 1.95 v 3 v host supply; v ss =0v [1] 3.0 - 3.6 v p tot total power dissipation reader; i vdd(tx) = 100 ma; v bat =5.5v --420mw
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 35 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware [1] v ss represents v ss(pad) and v ss(tx) . [2] the antenna should be tuned not to exceed this curr ent limit (the detuning effect when coupling with another device must be taken into account). [3] external clock on nfc_clk_xtal1 must be low. [4] see ref. 10 for computing the power consumption as it depends on several parameters. [5] the antenna shall be tuned not to exceed the maximum of i bat . 13. thermal characteristics 14. characteristics 14.1 current consumption characteristics i bat battery supply current in hard power down state; v bat =3.6v; t=25c [3] -1014 ? a in standby state; v bat = 3.6 v; t = 25 c -20- ? a in monitor state; v bat = 2.75 v; t = 25 c --14 ? a in low-power polling loop; v bat =3.6v; t= 25 c; loop time = 500 ms [4] -150- ? a pcd mode at typical 3 v [5] --190ma i th(ilim) current limit threshold current current limiter on v dd(tx) pin; v dd(tx) =3.3v [5] -180-ma table 24. operating conditions ?continued symbol parameter conditions min typ max unit table 25. thermal characteristics symbol parameter conditions min typ max unit r th(j-a) thermal resistance from junction to ambient in free air with exposed pad soldered on a 4 layer jedec pcb -40- k/w table 26. current consumption characteristics for operating ambient temperature range symbol parameter conditions min typ max unit i bat battery supply current in hard power down state; v bat = 3.6 v; ven voltage = 0 v -1020 ? a in standby state; v bat =3.6v; [1] -2035 ? a in idle and listener modes; v bat =3.6v -4.55-ma in poller mode; v bat =3.6v -150-ma in monitor state; v bat =2.75v [2] -1020 ? a
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 36 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware [1] refer to section 10.1.2 for the description of the power modes. [2] this is the same value for v bat = 2.3 v when the monitor threshold is set to 2.3 v. 14.2 functional block elect rical characteristics 14.2.1 battery voltage monitor characteristics 14.2.2 reset via ven 14.2.3 power-up timings 14.2.4 power-down timings 14.2.5 i 2 c-bus timings here below are timings and frequency specifications. table 27. battery voltage monitor characteristics symbol parameter conditions min typ max unit v th threshold voltage set to 2.3 v 2.15 2.3 2.45 v set to 2.75 v 2.6 2.75 2.9 v v hys hysteresis voltage 100 150 200 mv table 28. reset timing symbol parameter conditions min typ max unit t w(ven) ven pulse width to reset 10 - - ? s t boot boot time - - 2.5 ms table 29. power-up timings symbol parameter conditions min typ max unit t t(vbat-ven) transition time from pin v bat to pin ven v bat , ven voltage = high 00.5- ms t t(vddpad-ven) transition time from pin v dd(pad) to pin ven v dd(pad) , ven voltage = high 00.5- ms t t(vbat-vddpad) transition time from pin v bat to pin v dd(pad) v bat , v dd(pad) = high 00.5- ms table 30. power-down timings symbol parameter conditions min typ max unit t vbat(l) time v bat low 20--ms
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 37 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware fig 30. i 2 c-bus timings table 31. high-speed mode i 2 c-bus timings specification symbol parameter conditions min max unit f clk(i2cscl) clock frequency on pin i2cscl i 2 c-bus scl; c b < 100 pf 03.4mhz t su;sta set-up time for a repeated start condition c b < 100 pf 160 - ns t hd;sta hold time (repeated) start condition c b < 100 pf 160 - ns t low low period of the scl clock c b < 100 pf 160 - ns t high high period of the scl clock c b < 100 pf 60 - ns t su;dat data set-up time c b < 100 pf 10 - ns t hd;dat data hold time c b < 100 pf 0 - ns t r(i2csda) rise time on pin i2csda i 2 c-bus sda; c b < 100 pf 10 80 ns t f(i2csda) fall time on pin i2csda i 2 c-bus sda; c b < 100 pf 10 80 ns v hys hysteresis voltage schmitt trigger inputs; c b < 100 pf 0.1v dd(pad) -v table 32. fast mode i 2 c-bus timings specification symbol parameter conditions min max unit f clk(i2cscl ) clock frequency on pin i2cscl i 2 c-bus scl; c b < 400 pf 0 400 khz t su;sta set-up time for a repeated start condition c b < 400 pf 600 - ns t hd;sta hold time (repeated) start condition c b < 400 pf 600 - ns t low low period of the scl clock c b < 400 pf 1.3 - ? s t high high period of the scl clock c b < 400 pf 600 - ns t su;dat data set-up time c b < 400 pf 100 - ns t hd;dat data hold time c b < 400 pf 0 900 ns v hys hysteresis voltage schmitt trigger inputs; c b < 400 pf 0.1v dd(pad) -v aaa-017006 i2csda i2cscl t r(i2csda) t hd;dat t su;dat t low t high t hd;sta t su;sta t f(i2csda)
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 38 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 14.3 pin characteristics 14.3.1 nfc_clk_xtal1 and nfc_clk_xtal2 pins characteristics 14.3.2 ven input pin characteristics table 33. input clock characteristics on nfc_clk_xtal1 when using pll symbol parameter conditions min typ max unit v i(p-p) peak-to-peak input voltage 0.2 - 1.8 v ? duty cycle 35 - 65 % table 34. pin characteristics for nfc_clk_xtal1 when pll input symbol parameter conditions min typ max unit i ih high-level input current v i =v dd ? 1- +1 ? a i il low-level input current v i =0v ? 1- +1 ? a v i input voltage - - v dd v v i(clk)(p-p) peak-to-peak clock input voltage 200 - - mv c i input capacitance all power modes - 2 - pf table 35. pin characteristics for 27.12 mhz crystal oscillator symbol parameter conditions min typ max unit c i(nfc_clk_xtal1) nfc_clk_xtal1 input capacitance v dd =1.8v - 2 - pf c i(nfc_clk_xtal2) nfc_clk_xtal2 input capacitance -2-pf table 36. pll accuracy symbol parameter conditions min typ max unit f o(acc) output frequency accuracy deviation added to nfc_clk_xtal1 frequency on rf frequency generated; worst case whatever input frequency ? 50 - +50 ppm table 37. ven input pin characteristics symbol parameter conditions min typ max unit v ih high-level input voltage 1.1 - v bat v v il low-level input voltage 0 - 0.4 v i ih high-level input current ven voltage = v bat ? 1- +1 ? a i il low-level input current ven voltage = 0 v ? 1- +1 ? a c i input capacitance - 5 - pf
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 39 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 14.3.3 pin characteristics for irq and clk_req [1] activated in hpd and monitor states. 14.3.4 input pin characteristics for rxn and rxp table 38. pin characteristics for irq and clk_req symbol parameter conditions min typ max unit v oh high-level output voltage i oh <3ma v dd(pad) ? 0.4 - v dd(pad) v v ol low-level output voltage i ol <3ma 0 - 0.4 v c l load capacitance - - 20 pf t f fall time c l =12pf max high speed 1 - 3.5 ns slow speed 2 - 10 ns t r rise time c l =12pf max high speed 1 - 3.5 ns slow speed 2 - 10 ns r pd pull-down resistance [1] 0.35 - 0.85 m ? table 39. input pin characteristics for rxn and rxp symbol parameter conditions min typ max unit v rxn(i) rxn input voltage 0 - v dd v v rxp(i) rxp input voltage 0 - v dd v c i(rxn) rxn input capacitance - 12 - pf c i(rxp) rxp input capacitance - 12 - pf z i(rxn-vddmi d) input impedance between rxn and v dd(mid) reader, card and p2p modes 0- 15k ? z i(rxp-vddmid ) input impedance between rxp and v dd(mid) reader, card and p2p modes 0- 15k ? v i(dyn)(rxn) rxn dynamic input voltage miller coded 106 kbit/s - 150 200 mv(p-p) 212 kbit/s to 424 kbit/s - 150 200 mv(p-p) v i(dyn)(rxp) rxp dynamic input voltage miller coded 106 kbit/s - 150 200 mv(p-p) 212 kbit/s to 424 kbit/s - 150 200 mv(p-p) v i(dyn)(rxn) rxn dynamic input voltage manchester, nrz or bpsk coded; 106 kbit/s to 848 kbit/s - 150 200 mv(p-p) v i(dyn)(rxp) rxp dynamic input voltage manchester, nrz or bpsk coded; 106 kbit/s to 848 kbit/s - 150 200 mv(p-p)
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 40 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 14.3.5 output pin characteristics for tx1 and tx2 14.3.6 input pin characteristics for i2cadr0 and i2cadr1 v i(dyn)(rxn) rxn dynamic input voltage all data coding; 106 kbit/s to 848 kbit/s v dd - - v(p-p) v i(dyn)(rxp) rxp dynamic input voltage all data coding; 106 kbit/s to 848 kbit/s v dd - - v(p-p) v i(rf) rf input voltage rf input voltage detected; initiator modes 100 - mv(p-p) table 39. input pin characteristics for rxn and rxp ?continued symbol parameter conditions min typ max unit table 40. output pin characteristics for tx1 and tx2 symbol parameter conditions min typ max unit v oh high-level output voltage v dd(tx) = 3.3 v and i oh =30ma; pmos driver fully on v dd(tx) ? 150 - - mv v ol low-level output voltage v dd(tx) = 3.3 v and i ol =30ma; nmos driver fully on --200mv table 41. output resistance for tx1 and tx2 symbol parameter conditions min typ max unit r ol low-level output resistance v dd(tx) ? 100 mv; cwgsn = 01h --85 ? r ol low-level output resistance v dd(tx) ? 100 mv; cwgsn = 0fh --5 ? r oh high-level output resistance v dd(tx) ? 100 mv - - 4 ? table 42. input pin characteri stics for i2cadr0 and i2cadr1 symbol parameter conditions min typ max unit v ih high-level input voltage 0.65v dd(pad) -v dd(pad) v v il low-level input voltage 0 - 0.35v dd(pad) v i ih high-level input current v i =v dd(pad) ? 1-+1 ? a i il low-level input current v i =0v ? 1-+1 ? a c i input capacitance - 5 - pf
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 41 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 14.3.7 pin characteristics for i2csda and i2cscl [1] only for pin i2csda as i2cscl is only used as input. 14.3.8 v dd pin characteristic table 43. pin characteristics for i2csda and i2cscl symbol parameter conditions min typ max unit v ol low-level output voltage i ol <3ma [1] 0-0 . 4v c l load capacitance - - 10 pf t f fall time c l = 100 pf; rpull-up = 2 k ? ; standard and fast mode [1] 30 - 250 ns t f fall time c l = 100 pf; rpull-up = 1 k ? ; high-speed mode [1] 80 - 110 ns t r rise time c l = 100 pf; rpull-up = 2 k ? ; standard and fast mode [1] 30 - 250 ns c l = 100 pf; rpull-up = 1 k ? ; high-speed mode [1] 10 - 100 ns v ih high-level input voltage 0.7v dd(pad) -v dd(pad) v v il low-level input voltage 0 - 0.3v dd(pad) v i ih high-level input current v i =v dd(pad) ; high impedance ? 1-+1 ? a i il low-level input current v i =0v; high impedance ? 1-+1 ? a c i input capacitance - 5 - pf table 44. electrical characteristic of v dd symbol parameter conditions min typ max unit v dd v dd supply voltage v ss = 0v 1.65 1.8 1.95 v
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 42 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 15. package outline fig 31. package outline, hvqfn40, sot618-1, msl3 references outline version european projection issue date iec jedec jeita sot618-1 mo-220 sot618-1_po 02-10-22 13-11-05 unit mm max nom min 1.00 0.05 0.2 6.1 4.25 6.1 0.4 a (1) dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn40: plastic thermal enhanced very thin uad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm sot618-1 a 1 b 0.30 cd (1) d h e (1) e h 4.10 ee 1 e 2 lvw 0.05 y 0.05 y 1 0.1 0.85 0.02 6.0 4.10 6.0 0.21 0.3 3.95 0.80 0.00 5.9 3.95 5.9 0.18 0.5 4.5 0.5 4.25 4.5 0.1 e e 1/2 e 1/2 e y terminal 1 index area a a 1 c l e h d h b 11 20 40 31 30 21 10 1 d e terminal 1 index area 0 2.5 5 mm scale e 1 ac c b v w c y 1 c e 2 x detail x b a
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 43 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 44 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 16.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 32 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 4 5 and 46 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 32 . table 45. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 46. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 45 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 32. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 46 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 17. abbreviations table 47. abbreviations acronym description api application programming interface ask amplitude shift keying ask modulation index the ask modulation index is defined as the voltage ratio (vmax - vmin)/ (vmax + vmin) ? 100% automatic device discovery detect and recognize any nfc peer devic es (initiator or target) like: nfc initiator or target, iso/iec 14443-3, -4 type a&b picc, mifare standard and ultralight picc, iso/iec 15693 vicc bpsk bit phase shift keying card emulation the ic is capable of handling a picc emulation on the rf interface including part of the protocol management. the a pplication handling is done by the host controller dep data exchange protocol dsldo dual supplied ldo fw firmware hpd hard power down ldo low drop out lfo low frequency oscillator mosfet metal oxide semiconductor field effect transistor msl moisture sensitivity level nci nfc controller interface nfc near field communication nfcc nfc controller, PN7150 in this data sheet nfc initiator initiator as defined in iso/ie c 18092 or ecma 340: nfcip-1 communication nfcip nfc interface and protocol nfc target target as defined in iso/iec 18092 or ecma 340: nf cip-1 communication nrz non-return to zero p2p peer to peer pcd proximity coupling device. definition for a card reader/writer device according to the iso/iec 14 443 specification or mifare pcd -> picc communication flow between a pcd and a picc according to the iso/iec 14443 specification or mifare picc proximity interface coupling card. definition for a contactless smart card according to the iso/iec 14 443 specification or mifare picc-> pcd communication flow between a picc and a pcd according to the iso/iec 14443 specification or mifare pmos p-channel mosfet pmu power management unit psl parameter selection txldo transmitter ldo um user manual
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 47 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware vcd vicinity coupling device. definition for a reader/writer device according to the iso/iec 15693 specification vco voltage controlled oscillator vicc vicinity integrated circuit card wuc wake-up counter table 47. abbreviations ?continued acronym description
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 48 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 18. references [1] nfc forum device requirements ? v1.3 [2] nfc controller interface ( nci) technical specification ? v1.0 [3] iso/iec 14443 ? parts 2: 2001 cor 1 2007 (01/11/2007), part 3: 2001 cor 1 2006 (01/09/2006) and part 4: 2nd edition 2008 (15/07/2008) [4] i 2 c specification ? i 2 c specification, um10204 rev4 (13/02/2012) [5] PN7150 user manual ? um10936 PN7150 user manual [6] PN7150 hardware design guide ? an11756 PN7150 hardware design guide [7] PN7150 antenna design and matching guide ? an11755 PN7150 antenna design and matching guide [8] iso/iec 18092 (nfcip-1) ? edition, 15/032013. this is similar to ecma 340. [9] iso/iec15693 ? part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001) [10] PN7150 low-power mode configuration ? an11757 PN7150 low-power mode configuration [11] iso/iec 21481 (nfcip-2) ? edition, 01/07/2012. this is similar to ecma 352.
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 49 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 19. revision history table 48. revision history document id release date data sheet status change notice supersedes PN7150 v3.3 20160704 product data sheet - PN7150 v3.2 modifications: ? figure 1 : updated. ? section 10.7.1.4 : updated. ? section 10.7.3 : updated. PN7150 v3.2 201600525 product data sheet - PN7150 v3.1 PN7150 v3.1 20160511 product data sheet - PN7150 v3.0 PN7150 v3.0 20151209 product data sheet - PN7150 v2.1 PN7150 v2.1 20151127 preliminary data sheet - PN7150 v2.0 PN7150 v2.0 20150701 preliminary data sheet - PN7150 v1.2 PN7150 v1.2 20150625 objective data sheet - PN7150 v1.1 PN7150 v1.1 20150212 objective data sheet - PN7150 v1.0 PN7150 v1.0 20150129 objective data sheet - - modifications: ? initial version
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 50 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 51 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 20.4 licenses 20.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. desfire ? is a trademark of nxp semiconductors n.v. mifare ? is a trademark of nxp b.v. mifare classic ? is a trademark of nxp b.v. mifare ultralight ? is a trademark of nxp b.v. icode and i-code ? are trademarks of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with iso/iec 14443 type b functionality this nxp semiconductors ic is iso/iec 14443 type b software enabled and is licensed under innovatron?s contactless card patents license for iso/iec 14443 b. the license includes the right to use the ic in systems and/or end-user equipment. ratp/innovatron technology purchase of nxp ics with nfc technology purchase of an nxp semiconductors ic that complies with one of the near field communication (nfc) standards iso/iec 18092 and iso/iec 21481 does not convey an implied license unde r any patent right infringed by implementation of any of those standards. purchase of nxp semiconductors ic does not include a license to any nxp patent (or other ip right) covering combinations of those products with other products, whether hardware or software.
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 52 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 22. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .3 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .4 table 3. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 5. system power modes description . . . . . . . . . .10 table 6. system power modes configuration . . . . . . . . .10 table 7. system power modes description . . . . . . . . . .10 table 8. PN7150 power states . . . . . . . . . . . . . . . . . . . 11 table 9. functional modes in active state . . . . . . . . . . .12 table 10. functionality for i 2 c-bus interface . . . . . . . . . .15 ta b l e 11 . i 2 c-bus interface addressing . . . . . . . . . . . . . .15 table 12. crystal requirements . . . . . . . . . . . . . . . . . . . .16 table 13. pll input requirements . . . . . . . . . . . . . . . . . .17 table 14. overview for iso/iec 14443a/mifare reader/writer communication mode . . . . . . . .26 table 15. overview for felica reader/writer communication mode . . . . . . . .27 table 16. overview for iso/iec 14443b reader/writer communication mode . . . . . . . . . . . . . . . . . . .27 table 17. communication overview for nfc forum t5t r/w mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 18. overview for active communication mode . . . .30 table 19. overview for passive communication mode . .31 table 20. overview for nfc forum t4t, iso/iec 14443a card mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 21. overview for nfc forum t4t, iso/iec 14443b card mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 22. overview for nfc forum t3t, sony felica card mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 23. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .34 table 24. operating conditions . . . . . . . . . . . . . . . . . . . .34 table 25. thermal characteristics . . . . . . . . . . . . . . . . . .35 table 26. current consumption characteristics for operating ambient temperature range . . . . . . . . . . . . . . .35 table 27. battery voltage monitor characteristics . . . . . .36 table 28. reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 29. power-up timings . . . . . . . . . . . . . . . . . . . . . . .36 table 30. power-down timings . . . . . . . . . . . . . . . . . . . .36 table 31. high-speed mode i 2 c-bus timings specification . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 32. fast mode i 2 c-bus timings specification . . . . .37 table 33. input clock characteristics on nfc_clk_xtal1 when using pll . . . . . . . . . . . . . . . . . . . . . . . .38 table 34. pin characteristics for nfc_clk_xtal1 when pll input . . . . . . . . . . . . . . . . . . . . . . . .38 table 35. pin characteristics for 27.12 mhz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 36. pll accuracy . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 37. ven input pin characteristics . . . . . . . . . . . . . .38 table 38. pin characteristics for irq and clk_req . . .39 table 39. input pin characteristics for rxn and rxp . . .39 table 40. output pin characteristics for tx1 and tx2 . . .40 table 41. output resistance for tx1 and tx2 . . . . . . . . .40 table 42. input pin characteristics for i2cadr0 and i2cadr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 43. pin characteristics for i2csda and i2cscl. . .41 table 44. electrical characteristic of v dd . . . . . . . . . . . . 41 table 45. snpb eutectic process (from j-std-020d) . . . 44 table 46. lead-free process (from j-std-020d) . . . . . . 44 table 47. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 48. revision history . . . . . . . . . . . . . . . . . . . . . . . . 49
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 53 of 55 nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 23. figures fig 1. PN7150 transmission modes . . . . . . . . . . . . . . . . .2 fig 2. PN7150 package marking (top view) . . . . . . . . . . .4 fig 3. PN7150 block diagram . . . . . . . . . . . . . . . . . . . . .6 fig 4. pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 fig 5. PN7150 connection . . . . . . . . . . . . . . . . . . . . . . . .9 fig 6. system power mode diagram . . . . . . . . . . . . . . .10 fig 7. polling loop: all phases enabled . . . . . . . . . . . . .13 fig 8. polling loop: low-power rf polling. . . . . . . . . . . .14 fig 9. 27.12 mhz crystal oscillator connection. . . . . . . .16 fig 10. input reference phase noi se characteristics . . . .17 fig 11. pmu functional diagram . . . . . . . . . . . . . . . . . . .18 fig 12. v bat1 = v bat2 (between 2.3 v and 5.5 v) . . . . . .19 fig 13. v dd(tx) offset behavior. . . . . . . . . . . . . . . . . . . . .20 fig 14. v dd(tx) behavior when PN7150 is in standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 fig 15. v bat1 = 5 v, v bat2 between 2.3 v and 5.5 v . . . .21 fig 16. v dd(tx) behavior when PN7150 is supply using external supply on v bat1 . . . . . . . . . . . . . . . . . . .21 fig 17. battery voltage monitor prin ciple . . . . . . . . . . . . .22 fig 18. resetting PN7150 via ven pin . . . . . . . . . . . . . .23 fig 19. v bat is set up before v dd(pad) . . . . . . . . . . . . . . .23 fig 20. v dd(pad) and v bat are set up in the same time . .24 fig 21. v dd(pad) is set up or cut-off after PN7150 has been enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 22. PN7150 power-down sequence. . . . . . . . . . . . . .25 fig 23. iso/iec 14443a/mifare reader/writer communication mode diagram. . . . . . . . . . . . . . .26 fig 24. felica reader/writ er communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 fig 25. iso/iec 14443b reader/writer communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .27 fig 26. r/w mode for nfc forum t5t communication diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 fig 27. nfcip-1 communication mode . . . . . . . . . . . . . .29 fig 28. active communication mode . . . . . . . . . . . . . . . .30 fig 29. passive communication mode . . . . . . . . . . . . . . .31 fig 30. i 2 c-bus timings . . . . . . . . . . . . . . . . . . . . . . . . . .37 fig 31. package outline, hvqfn40, sot618-1, msl3. .42 fig 32. temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
PN7150 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights rese rved. product data sheet rev. 3.3 ? 4 july 2016 54 of 55 continued >> nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware 24. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general description . . . . . . . . . . . . . . . . . . . . . . 1 3 features and benefits . . . . . . . . . . . . . . . . . . . . 2 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 ordering information . . . . . . . . . . . . . . . . . . . . . 4 7 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 9.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 functional description . . . . . . . . . . . . . . . . . . . 8 10.1 system modes . . . . . . . . . . . . . . . . . . . . . . . . . 9 10.1.1 system power modes . . . . . . . . . . . . . . . . . . . . 9 10.1.2 PN7150 power states . . . . . . . . . . . . . . . . . . . 10 10.1.2.1 monitor state . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1.2.2 hard power down (hpd) state. . . . . . . . . . . . 11 10.1.2.3 standby state . . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1.2.4 active state . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10.1.2.5 polling loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10.2 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . 14 10.3 host interface . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.3.1 i 2 c-bus interface. . . . . . . . . . . . . . . . . . . . . . . 15 10.3.1.1 i 2 c-bus configuration . . . . . . . . . . . . . . . . . . . 15 10.4 PN7150 clock concept . . . . . . . . . . . . . . . . . . 15 10.4.1 27.12 mhz quartz oscillator . . . . . . . . . . . . . . 16 10.4.2 integrated pll to make use of external clock 16 10.4.3 low-power 40 mhz 2.5 % oscillator . . . . . . 18 10.4.4 low-power 380 khz oscillator. . . . . . . . . . . . . 18 10.5 power concept . . . . . . . . . . . . . . . . . . . . . . . . 18 10.5.1 pmu functional description . . . . . . . . . . . . . . . 18 10.5.2 dsldo: dual supply ldo . . . . . . . . . . . . . . . 18 10.5.3 txldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.5.3.1 configuration 1: su pply connection in case the battery is used to generate rf field . . . . . . . . 19 10.5.3.2 configuration 2: supply connection in case a 5 v supply is used to generate rf field with the use of txldo . . . . . . . . . . . . . . . . . . 20 10.5.3.3 txldo limiter . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.5.4 battery voltage monitor. . . . . . . . . . . . . . . . . . 21 10.6 reset concept. . . . . . . . . . . . . . . . . . . . . . . . . 22 10.6.1 resetting PN7150 . . . . . . . . . . . . . . . . . . . . . 22 10.6.2 power-up sequences . . . . . . . . . . . . . . . . . . . 23 10.6.2.1 v bat is set up before v dd(pad) . . . . . . . . . . . . 23 10.6.2.2 v dd(pad) and v bat are set up in the same time 23 10.6.2.3 PN7150 has been enabled before v dd(pad) is set up or before v dd(pad) has been cut off . . . . . . 24 10.6.3 power-down sequence . . . . . . . . . . . . . . . . . 25 10.7 contactless interface unit . . . . . . . . . . . . . . . 25 10.7.1 reader/writer communication modes . . . . . . 25 10.7.1.1 iso/iec 14443a/mifare and jewel/topaz pcd communication mode. . . . . . . . . . . . . . . . . . . 25 10.7.1.2 felica pcd communication mode. . . . . . . . . 26 10.7.1.3 iso/iec 14443b pc d communication mode. 27 10.7.1.4 r/w mode for nfc foru m type 5 tag . . . . . . 28 10.7.2 iso/iec 18092, ecma 340 nfcip-1 communication modes . . . . . . . . . . . . . . . . . . 29 10.7.2.1 active communication mode. . . . . . . . . . . . 29 10.7.2.2 passive communication mode . . . . . . . . . . . . 30 10.7.2.3 nfcip-1 framing and coding . . . . . . . . . . . . . 31 10.7.2.4 nfcip-1 protocol support . . . . . . . . . . . . . . . 31 10.7.3 card communication modes . . . . . . . . . . . . . 32 10.7.3.1 nfc forum t4t, iso/iec 14443acard mode. 32 10.7.3.2 nc forum t4t, iso/iec 14443b card mode . 32 10.7.3.3 nfc forum t3t, sony felica card mode. . . . 33 10.7.4 frequency interoperability . . . . . . . . . . . . . . . 33 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34 12 recommended operating conditions . . . . . . 34 13 thermal characteristics . . . . . . . . . . . . . . . . . 35 14 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 14.1 current consumption characteristics . . . . . . . 35 14.2 functional block electrical characteristics . . . 36 14.2.1 battery voltage monitor characteristics . . . . . 36 14.2.2 reset via ven . . . . . . . . . . . . . . . . . . . . . . . . 36 14.2.3 power-up timings . . . . . . . . . . . . . . . . . . . . . . 36 14.2.4 power-down timing s. . . . . . . . . . . . . . . . . . . . 36 14.2.5 i 2 c-bus timings. . . . . . . . . . . . . . . . . . . . . . . . 36 14.3 pin characteristics . . . . . . . . . . . . . . . . . . . . . 38 14.3.1 nfc_clk_xtal1 and nfc_clk_xtal2 pins characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 14.3.2 ven input pin characteristics . . . . . . . . . . . . . 38 14.3.3 pin characteristics for irq and clk_req . 39 14.3.4 input pin characteristics for rxn and rxp . . 39 14.3.5 output pin characteristics for tx1 and tx2 . . 40 14.3.6 input pin characteristics for i2cadr0 and i2cadr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 14.3.7 pin characteristics for i2csda and i2cscl . 41 14.3.8 v dd pin characteristic. . . . . . . . . . . . . . . . . . . 41 15 package outline. . . . . . . . . . . . . . . . . . . . . . . . 42 16 soldering of smd packages . . . . . . . . . . . . . . 43 16.1 introduction to soldering. . . . . . . . . . . . . . . . . 43 16.2 wave and reflow soldering. . . . . . . . . . . . . . . 43 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43 16.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 44
nxp semiconductors PN7150 full nfc forum-compliant contro ller with integrated firmware ? nxp semiconductors n.v. 2016. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 4 july 2016 document identifier: PN7150 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 46 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . 49 20 legal information. . . . . . . . . . . . . . . . . . . . . . . 50 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 50 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 20.5 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 51 21 contact information. . . . . . . . . . . . . . . . . . . . . 51 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 24 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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